Computer Science • Digital Logic & Circuits

Logic Gate Deflector

Dynamic topology circuits require instant digital logic synthesis. Insert logic gates to deflect signal errors and meet the multi-vector test matrix requirements before your shield collapses.

Learning objectiveDigital Circuits · Boolean Logic

Analyze multi-stage logic gate cascades, deduce boolean transformations across dynamic wire topologies, and satisfy multi-vector signal constraints under strict real-time conditions.

By completing each wave you will master: fundamental logic gate operators (AND, OR, XOR, NAND, NOR, XNOR); intermediate bus signals ($Q_1$) and branching inputs; and real-time truth matrix evaluation.

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  • Observe the input bus signals (A, B, C) and target output Y across the required test vectors.
  • Click a stage slot (G1 or G2) to select it, then pick a logic gate from the bottom palette.
  • Dynamic wires update in real-time, displaying signal flow ($1$ = active cyan, $0$ = dark wire).
  • Pass all signal test vectors simultaneously to complete the wave and store remaining time as bonus score.
  • Failing verification or letting the timer expire reduces shield capacity. Game ends at 0% shield.

Logic Gate Deflector — Key Terms

Key concepts and translations across English, te reo Māori, Simplified Chinese (中文) and Korean (한국어).

EnglishTe reo Māori中文(简体)한국어What it means on this page

On the te reo Māori column. Terms marked as gaps have no attested equivalent in the sources checked — Karaitiana Taiuru's Dictionary of Māori Computer and Social Media Terms, Paekupu, the Reserve Bank's te reo financial glossary and Te Aka. No coinage is printed as though it were established; where a class needs one, commission it from Te Taura Whiri i te Reo Māori and credit the translator. Te reo Māori is not italicised and takes no plural "s".