Computer Science • Processor Architecture

Run the CPU

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You are the control unit. Every value a program uses has to be moved by you — from the program counter to the memory address register, out of memory, into the current instruction register and on to the ALU. Run each program through the fetch–decode–execute cycle before the clock runs out.

Learning objectiveVon Neumann architecture · F–E cycle

Describe the role of each register in a Von Neumann processor and carry out the fetch–decode–execute cycle, writing each step in register transfer notation.

By the end of a game you should be able to: explain the stored program concept; state what the PC, MAR, MDR, CIR, ACC and status register hold; describe how the address bus, data bus and control bus are used during a fetch; and trace how LOAD, STORE, ADD, SUB, MOV and jump instructions are executed.

  • Drag a value from one register (or the highlighted memory row) onto another to copy it — or tap the source, then tap where it goes.
  • Fetch: drag the PC to the MAR, the highlighted memory contents to the MDR, then the MDR to the CIR. Press +1 on the PC once in every cycle, at any point after the PC has been copied.
  • Press DECODE, then hover the opcode to see what it does. Drag the operand where it's needed.
  • For ALU instructions, fill inputs A (always the ACC) and B, then press RUN ME.
  • Each correct step scores points; a whole instruction or program without a mistake scores a bonus. A wrong step costs clock ticks.
  • Every program adds ticks to the clock and finishing one adds a few more — but the clock gets faster each time. Run out of ticks and the CPU stops.
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The stored program concept

In a Von Neumann computer, instructions and data are stored together in the same main memory, both as binary. The processor can't tell them apart by looking — a byte is an instruction only because the program counter pointed at it and it was fetched into the CIR.

Instructions are fetched from memory one at a time and executed in sequence, unless an instruction (such as a jump) changes the program counter. Because instructions and data share one memory and one set of buses, only one can be moved at a time — the Von Neumann bottleneck.

Inside the CPU

PC
Program counter — the address of the next instruction to fetch.
MAR
Memory address register — the address about to be read from or written to. It drives the address bus.
MDR
Memory data register — the data just read from memory, or about to be written. It sits on the data bus.
CIR
Current instruction register — the instruction being decoded and executed, split into opcode and operand.
ACC
Accumulator — holds the result of each calculation the ALU does.
SR
Status register — flags set by the ALU: Z (zero), N (negative), C (carry) and V (overflow).
R0–R7
General-purpose registers — fast storage for values a program is working with, so it doesn't have to go back to memory.
ALU
Arithmetic logic unit — does the calculations and comparisons. Here, input A always takes the ACC.
CU
Control unit — decodes each instruction and sends control signals to carry it out. In this game, that's you.

The address bus carries addresses one way, from the MAR to memory. The data bus carries data both ways between the MDR and memory. The control bus carries signals such as memory read and write, and the clock keeps every step in time.

The fetch–decode–execute cycle

In register transfer notation, ← means "is copied into", [X] means "the contents of X", and [[MAR]] means "the contents of the memory location whose address is in the MAR".

  1. MAR ← [PC]the address of the next instruction is copied to the MAR
  2. PC ← [PC] + 1the PC is incremented, ready for the next cycle
  3. MDR ← [[MAR]]the instruction at that address travels over the data bus to the MDR
  4. CIR ← [MDR]the instruction is copied to the CIR
  5. Decodethe control unit splits the CIR into opcode and operand and works out what to do
  6. Executethe steps for that instruction — which might use the MAR and MDR again, the ALU, or the PC

Steps 1 and 2 can happen at the same time in a real CPU. Here you can press +1 any time after step 1, as long as it happens once before the cycle ends.

Instruction set

Each 8-bit instruction is a 4-bit opcode followed by a 4-bit operand — a memory address (0–15) or a register number (0–7).

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Run the CPU — Key Terms

Key concepts and translations across English, te reo Māori, Simplified Chinese (中文) and Korean (한국어).

EnglishTe reo Māori中文（简体）한국어What it means on this page

On the te reo Māori column. Terms marked as gaps have no attested equivalent in the sources checked — Karaitiana Taiuru's Dictionary of Māori Computer and Social Media Terms, Paekupu, the Reserve Bank's te reo financial glossary and Te Aka. No coinage is printed as though it were established; where a class needs one, commission it from Te Taura Whiri i te Reo Māori and credit the translator. Te reo Māori is not italicised and takes no plural "s".